Through-Silicon Vias
Vertical electrical connections etched through silicon dies or interposers for dense 3D and 2.5D chip integration.
Core metadata
- ID: through_silicon_vias
- Era: Modern
- First known date: 1980 (decade)
- Region: Japan, United States, and global semiconductor packaging
- Review status: source_checked
- Maturity: established
Prerequisites
Dependents
- Advanced Semiconductor Packaging 2.5D/3D (advanced_semiconductor_packaging_2_5d_3d)
- High Bandwidth Memory (high_bandwidth_memory_hbm)
Fields
Field lanes
- Semiconductors & Integrated Circuits: Packaging & Interconnect
Node sources
- Metrology Needs for 2.5D/3D Interconnect (NIST, 2014, official_agency) • Supports: node, maturity
- 3DFabric (TSMC, 2026, generic_overview) • Supports: node, maturity
Prerequisite edge evidence
Edge/source evidence summary:
- Prerequisite edges: 2
- Average edge confidence: 75%
- Prerequisite sources: 2
- expert_inference: 2
| Prerequisite | Type | Confidence | Evidence level | Note | Sources |
|---|---|---|---|---|---|
| Photolithography (photolithography) | required | 82% | expert_inference | Photolithography is modeled as a necessary component or method for this technology in the current graph. |
|
| Plasma Etching (plasma_etching) | enabling | 68% | expert_inference | Plasma Etching provides a capability that enables this technology without being the only possible path. |
|
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