High Bandwidth Memory
Stacked DRAM memory using through-silicon vias and very wide interfaces for high-throughput GPUs and accelerators.
Core metadata
- ID: high_bandwidth_memory_hbm
- Era: Modern
- First known date: 2010 (decade)
- Region: Global / multiple regions
- Review status: source_checked
- Maturity: established
Prerequisites
- Advanced Semiconductor Packaging 2.5D/3D (advanced_semiconductor_packaging_2_5d_3d)
- DRAM Memory (dram_memory)
- Through-Silicon Vias (through_silicon_vias)
Dependents
Fields
Field lanes
- Semiconductors & Integrated Circuits: Memory & Storage
Node sources
- JEDEC Publishes HBM3 Update to High Bandwidth Memory Standard (JEDEC / Business Wire, 2022, official_agency) • Supports: node, maturity
- 3DFabric (TSMC, 2026, official_agency) • Supports: node, maturity
Prerequisite edge evidence
Edge/source evidence summary:
- Prerequisite edges: 3
- Average edge confidence: 73%
- Prerequisite sources: 3
- expert_inference: 3
| Prerequisite | Type | Confidence | Evidence level | Note | Sources |
|---|---|---|---|---|---|
| DRAM Memory (dram_memory) | enabling | 68% | expert_inference | DRAM Memory provides a capability that enables this technology without being the only possible path. |
|
| Through-Silicon Vias (through_silicon_vias) | enabling | 68% | expert_inference | Through-Silicon Vias provides a capability that enables this technology without being the only possible path. |
|
| Advanced Semiconductor Packaging 2.5D/3D (advanced_semiconductor_packaging_2_5d_3d) | required | 82% | expert_inference | Advanced Semiconductor Packaging 2.5D/3D is modeled as a necessary component or method for this technology in the current graph. |
|
This page is generated from canonical era JSON and is indexable by URL.