Gate-All-Around Nanosheet Transistors
Transistors whose gates wrap around stacked nanosheet channels for continued logic scaling beyond FinFETs.
Core metadata
- ID: gate_all_around_nanosheet_transistors
- Era: Modern
- First known date: 2017 (exact)
- Region: IBM Research Albany and global leading-edge semiconductor foundries
- Review status: source_checked
- Maturity: emerging
Prerequisites
- Atomic Layer Deposition (atomic_layer_deposition)
- EUV Lithography (euv_lithography)
- FinFET Transistors (finfet_transistors)
Dependents
Fields
Field lanes
- Semiconductors & Integrated Circuits: Roadmap
Node sources
- Introducing the world's first 2 nm node chip (IBM Research, 2021, official_agency) • Supports: node, maturity, roadmap
- Samsung Begins Chip Production Using 3nm Process Technology With GAA Architecture (Samsung Semiconductor Global, 2022, official_agency) • Supports: node, maturity, roadmap
- Accelerating AI and HPC with Advanced Technologies (Intel Foundry, 2026, official_agency) • Supports: node, maturity, roadmap
Prerequisite edge evidence
Edge/source evidence summary:
- Prerequisite edges: 3
- Average edge confidence: 71%
- Prerequisite sources: 3
- expert_inference: 3
| Prerequisite | Type | Confidence | Evidence level | Note | Sources |
|---|---|---|---|---|---|
| FinFET Transistors (finfet_transistors) | historical_predecessor | 78% | expert_inference | FinFETs are the immediate scaling predecessor that GAA nanosheet devices are meant to move beyond, not a literal component of GAA nanosheets. |
|
| Atomic Layer Deposition (atomic_layer_deposition) | enabling | 68% | expert_inference | Atomic Layer Deposition provides a capability that enables this technology without being the only possible path. |
|
| EUV Lithography (euv_lithography) | enabling | 68% | expert_inference | EUV Lithography provides a capability that enables this technology without being the only possible path. |
|
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