Backside Power Delivery

Chip fabrication approach routing power through the back of the wafer to reduce front-side interconnect congestion and voltage droop.

Core metadata

Prerequisites

Dependents

Fields

Field lanes

Node sources

Prerequisite edge evidence

Edge/source evidence summary:

Prerequisite Type Confidence Evidence level Note Sources
Gate-All-Around Nanosheet Transistors (gate_all_around_nanosheet_transistors) commercial_or_scaling_dependency 76% primary_source Intel describes PowerVia and RibbonFET/GAA as co-introduced scaling technologies while also stating PowerVia was developed separately from transistor development.
Semiconductor Process Nodes (semiconductor_process_nodes) required 82% expert_inference Semiconductor Process Nodes is modeled as a necessary component or method for this technology in the current graph.
Chemical Mechanical Planarization (chemical_mechanical_planarization) enabling 68% expert_inference Chemical Mechanical Planarization provides a capability that enables this technology without being the only possible path.

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