Fan-Out Wafer-Level Packaging
Wafer-level package architecture that embeds known-good dies in a reconstituted wafer or panel and fans I/O outward through redistribution layers.
Core metadata
- ID: fan_out_wafer_level_packaging
- Era: Modern
- First known date: 2009 (exact)
- Region: Global semiconductor packaging industry
- Review status: source_checked
- Maturity: established
Prerequisites
Dependents
Fields
Field lanes
- Semiconductors & Integrated Circuits: Packaging & Interconnect
Node sources
- Heterogeneous Integration Roadmap (IEEE Electronics Packaging Society, 2026, review) • Supports: node, maturity
- Fan-Out Packaging (ASE, 2026, generic_overview) • Supports: node, maturity
- Integrated Fan-Out (InFO) Wafer Level Packaging (TSMC, 2026, generic_overview) • Supports: node, maturity
Prerequisite edge evidence
Edge/source evidence summary:
- Prerequisite edges: 2
- Average edge confidence: 81%
- Prerequisite sources: 5
- expert_inference: 1
- review: 1
| Prerequisite | Type | Confidence | Evidence level | Note | Sources |
|---|---|---|---|---|---|
| Integrated Circuits (Microchips) (integrated_circuits) | required | 88% | review | Fan-out wafer-level packaging embeds and reconnects known-good integrated-circuit dies; the packaged die is the component being integrated. |
|
| Photolithography (photolithography) | enabling | 74% | expert_inference | Fan-out packages use patterned redistribution layers; photolithography is an enabling process for those fine package-level interconnects. |
|
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